In keeping up with the demand for reducing the power consumption, the power supply voltage of a semiconductor device is decreasing in these days. For example, in the spec for the DDR2 SDRAM (Double Data Rate 2 Synchronous DRAM), the external voltage is set at 1.8V. Recently, to further reduce the power consumption, an internal voltage step-down circuit is used to provide an internal voltage lower than the external voltage. On the other hand, there is a demand for faster access to the semiconductor device. For example, in a synchronous DRAM, such as the above mentioned DDR2 SDRAM, an ultra-high speed memory access, exceeding 1 Gbps, is needed. To realize the faster access with the use of the internal power supply voltage, thus suppressed to an extremely low value, suppression of the power supply noise in the semiconductor device becomes crucial since the power supply noise within the semiconductor device is increased in the high-speed operation.
In Patent Document 1, there is disclosed a DRAM in which a power supply line L1 that delivers a reference potential Vcc1 to a sense circuit composed e.g., of an X-decoder and a sense amplifier is isolated from a power supply line L3 that delivers a reference potential Vcc2 to an output circuit composed of a read amplifier and an output buffer. These power lines are run by respective separate power supplies. Patent Document 1 states that potentials Vcc2 and Vcc1 are interconnected by a diode, and that, if the potential Vcc1 on the power supply line L1 is varied due to power consumption in the sense circuit, the power supply lines L1, L3 are electrically connected to each other. These potential variations on the power supply line L1 are dispersed in the power line L3 to suppress potential variations in the power supply line L1.
[Patent Document 1]
    JP Patent Kokai Publication No. JP-A-9-251777